FIELD OF THE INVENTION
The invention relates to semiconductor technology. More particularly, the invention pertains to a method for producing an EEPROM semiconductor structure with a resistor, a thin-film transistor, a capacitor, and a transistor.
It is a typical problem, in such semiconductor structures, that when a CMOS circuit is used, negative voltages have to be added onto a chip with a p-substrate, in which case the substrate must be kept at a zero potential. The same problem conversely arises with positive voltages, which have to be added onto an n-substrate.
In some applications, this problem can be solved by introducing a substrate bias. If a p-substrate is used, the substrate potential is shifted in the negative direction, and as a result the drain diodes of the NMOS in a CMOS inverter are merely biased positively compared to the substrate and are therefore operated in the blocking direction. A disadvantage here is the higher burden on the gate oxide from the additive negative substrate bias. The electrical properties, such as the NMOS on-state voltage and hence the drain current and performance, are dependent on the substrate voltage. Furthermore, the negative voltage must be generated on the chip.
If a negative polarization of the substrate cannot be allowed, then the NMOS transistors that connect the negative voltage can be placed in an isolated p-well. The isolation is achieved by means of a deeper n-well, which completely surrounds the p-well and which is blocked to the substrate at the same negative well bias. If an n-substrate is used, the opposite conductivity type must be used. However, producing such an additional, isolating well makes the overall process more complicated and expensive, and high-energy implantation is necessary.
In many processes in which the above-described problem arises, an additional polyplane and an interpolydielectric are generally processed along with the transistor polyplane. Examples of this are analog and memory processes.